Senior Engineer (Level 1)- Verification

Roles and Responsibilities: 

·       4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM. 

·       Strong knowledge of UVM, advance UVM,System Verilog. 

·       Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM. 

Understanding of complete functional verification cycle will be added advantage 

·       Must have executed at-least 1 to 2 SoC/IP Verification projects. 

·       Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required. 

·       Skills to debug RTL & testbench issues, test failures.  

·       Experience on verification closure by closing Coverage and bug reports 

·       Primarily knowledge of Script development and maintenance  

·       Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc