PD - Sr Staff - Physical Verification Lead | Signoff & DRC

Eliyan is building a proprietary die-to-die chiplet interconnect fabric for AI infrastructure at hyperscale.

Bay Area Full-time Posted 1mo ago semiconductorai infrastructurechiplets

ABOUT THE ROLE

As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.

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