SI/PI Intern

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a Signal Integrity / Power Integrity Intern, you will help design and validate the next generation of high-performance AI systems. You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed interfaces, extract channel models, and improve signal quality across our accelerator platforms.

This role provides hands-on experience with industry-leading tools and real-world challenges involving PCIe, Ethernet, high-speed SerDes channels, advanced packaging, and multi-board systems.

Key Responsibilities

• Signal Integrity Analysis

• Perform channel analysis for high-speed interfaces including PCIe, Ethernet, and other SerDes links. Extract and validate S-parameter models from package and PCB layouts. Analyze insertion loss, return loss, impedance discontinuities, and crosstalk. Generate channel compliance reports and support design reviews. Modeling & Simulation

• Build and validate 3D electromagnetic models using Ansys HFSS. Develop board and package channel models from ECAD design databases. Correlate simulation results with measurements and lab data. Support mixed package-board channel simulations and optimization.

• Partner with PCB layout, package, hardware, and ASIC teams to improve signal integrity. Identify root causes of channel degradation and propose design improvements. Contribute to SI design guidelines and best practices.

Representative Projects

• Extracting S-parameter models from package and board designs for PCIe channels.

• Building HFSS models of high-speed breakout regions and BGA transitions.

• Performing channel compliance analysis for Ethernet links.

• Investigating impedance discontinuities and optimizing via structures.

• Developing automated workflows for SI simulation and report generation.

You May Be a Good Fit If You Have

• Progress toward a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.

• Coursework or project experience in signal integrity, electromagnetics, RF, microwave engineering, or high-speed digital design.

• Familiarity with transmission line theory and S-parameters.

• Understanding of PCB stackups, routing, and high-speed design fundamentals.

• Strong analytical and debugging skills.

• Excellent communication and collaboration skills.

• Strong Candidates May Also Have

• Experience with Ansys HFSS, SIwave, ADS, CST, or similar simulation tools.

• Experience with PCIe, Ethernet, DDR, or other high-speed interfaces.

• Familiarity with Allegro, APD, ODB++, IPC2581, or other ECAD databases.

• Experience processing Touchstone files and channel metrics.

• Python scripting for simulation automation and data analysis.

• Experience with laboratory measurements using VNAs, oscilloscopes, or TDR equipment.

We encourage you to apply even if you do not believe you meet every qualification.

Program details

• 12-week paid internship

• Generous housing support for those relocating

• Daily lunch and dinner in our office

• Based at our office in San Jose, CA

• Direct mentorship from industry leaders and world-class engineers

• Opportunity to work on one of the most important problems of our time

For any questions, contact [email protected].

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.